免费的电子元器件数据手册查询系统 addbookmark

English China
数据表, 资料表, 数据手册, 零件,电子零件,集成电路,单片机,二极管,晶闸管,以及其他半导体产品信息
主页 | 功能分类 | 厂商列表 Bookmark and Share

Related keyword

  •   74ALVC125D-118 Datasheet
  •   74ALVC125D-118 Cross Reference
  •   74ALVC125D-118 Schematic
  •   74ALVC125D-118 Distributor
  •   74ALVC125D-118 Datenblatt
  •   74ALVC125D-118 RoHS
  •   74ALVC125D-118 Equivalent
  •   74ALVC125D-118 Application Notes
  •   74ALVC125D-118 Data Sheet
  •   74ALVC125D-118 component
  •   74ALVC125D-118 Fiche Technique
  •   74ALVC125D-118 Circuit
  • 74ALVC  -  系列元器件数据手册
    74ALVC125D-118  -  Quad buffer/line driver; 3-state  -  NXP Semiconductors(PHILIPS)  -  缓冲器


    General description
    The 74ALVC125 is a quad non-inverting buffer/line driver with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH on the nOE pin causes the outputs to assume a high-impedance OFF-state.

    Features
    n Wide supply voltage range from 1.65 V to 3.6 V
    n 3.6 V tolerant inputs/outputs
    n CMOS low power consumption
    n Direct interface with TTL levels (2.7 V to 3.6 V)
    n Power-down mode
    n Latch-up performance exceeds 250 mA
    n Complies with JEDEC standards:
    u JESD8-7 (1.65 V to 1.95 V)
    u JESD8-5 (2.3 V to 2.7 V)
    u JESD8B/JESD36 (2.7 V to 3.6 V)
    n ESD protection:
    u HBM JESD22-A114E exceeds 2000 V
    u MM JESD22-A 115-A exceeds 200 V



    点击查看 : 74ALVC125D-118.pdf   



    收藏本站 网站地图 联系我们
    版权所有© Ic-datasheet-pdf.com 2009-2012
    鲁ICP备12008433号-2
    Valid XHTML 1.0 Transitional